1. Field of the Invention L The present invention relates to an integrated circuit, and particularly to an integrated circuit in which the layout designing of a clock supplying circuit of the integrated circuit can be started independently of the layout designing of a logic circuit area of the integrated circuit.
2. Description of the Prior Art
For a conventional small scale integrated circuit, a single clock buffer having a large driving capability may be sufficient to supply clock signals for various loads such as gates and flip-flops connected to an output of the clock buffer. FIG. 1 shows a conventional clock supplying system for such a small scale integrated circuit. In the figure, a clock input pad 1 is connected to a single buffer 2 having a large driving capability for supplying clock signals for gates G1 and G2, a flip-flop FF1, an inverter I1, etc.
As the scale of integration of a circuit expands, it will be difficult for a single buffer to drive all loads connected to the buffer. To deal with this problem, an integrated circuit having a clock driving and supplying system shown in FIG. 2 has been developed. In the figure, a plurality of buffers 21, 31 to 34, 41 and 42 are arranged in a tree shape. The first-level buffer 21 drives the second-level buffers 31 to 34, which drive the buffers 41 and 42 of lower levels. Through these buffers, clock signals are supplied to loads such as gates G1 and G2 and flip-flops FF1 to FF8 connected to the buffers. In designing an integrated circuit employing such a clock dividing and supplying system, however, there is no established method where the buffers should be placed in the integrated circuit.
For example, an integrated circuit 5 of FIG. 3 has second-level buffers 31 to 36 placed in a logic circuit area 4 adjacent to circuit elements that require clock signals. Since the second-level buffers 31 to 36 are placed in the logic circuit area 4, the path of a wire l for connecting a first-level buffer 21 with the second-level buffers 31 to 36 cannot be determined until the layout of the logic circuit area 4 is completely designed. This raises a problem that the layout designing of a clock supplying circuit of correct drive timing cannot be started until the layout designing of the logic circuit area 4 is completed.